Home / CSE Branch / Digital Design through verilog HDL pdf Notes – DDTV pdf Notes

Digital Design through verilog HDL pdf Notes – DDTV pdf Notes

Digital Design through verilog HDL pdf Notes – DDTV pdf Notes

Digital Design through verilog HDL pdf Notes – DDTV Notes pdf – DDTV pdf Notes

DDTV Digital Design through verilog HDL pdf Notes JNTU

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DDTV:Complete Notes

DDTV:Unit 1 Notes

DDTV:Unit 2 Notes

DDTV:Unit 3 Notes

DDTV:Unit 4 Notes

DDTV:Unit 5 Notes

DDTV Old Material Links

DDTV:UNIT – 1

DDTV:UNIT – 2

DDTV:UNIT – 3

DDTV:UNIT – 4

DDTV:UNIT – 5

Unit I

  • Introduction to Verilog HDL: Verilog as HDL. Levels of Design description. Concurrency. Simulation and Synthesis.
  • Function Verification, System tasks. Programming Language interface, Module. Simulation and Synthesis tools

Unit II

  • Language Constructs and Conventions: Introduction. Keywords. Identifiers. White space Characters, Comments. Numbers,
  • Strings. Logic Values. Strengths. Data types. Scalars and vectors, parameters. operators.

Unit III

  • Gate Level Modeling: Introduction. AND Gate Primitive. Module structure. other gate primitives. illttstrative examples. tristate gates. array of instances of primitives.
  • Design of Flip —Flops with gate primitives. Delays. Strengths and Construction resolution. Net types. Design of basic circuit.

Unit IV

  • Behavioral Modeling: Introduction. Operations and assignments. functional bifurcation. ‘Initial’ construct. ‘always’ construct. Assignments with Delays. ‘wait‘ construct, multiple always block,
  • Designs at behavioral level. blocking and non- blocking assignments. the ‘case‘ statement. simulation flow “if” and ‘if-else’ constructs. ‘assign- de-assign’ construct. ‘repeat‘ construct. for loop.
  • ‘ the disable’ construct. ‘while loop‘. for ever loop. parallel blocks. ‘ f0rce- release, construct. Event.

Unit V

  • Modeling at Dataflow Level: Introduction. Continuous assignment structure. delays and continuous assignments. assignment to vectors. operators.
  • Switch level modeling: Basic transistor switches. CMOS switches. bi directional gates. time delays with switch primitives. instantiation with strengths‘ and ‘ delays’. strength contention with Trireg nets.

Unit VI

  • System Tasks. Functions and Compiler Directives: Parameters. Path delays. module parameters. system tasks and functions.
  • file based tasks and functions, computer directives. Hierarchical access. User defined Primitives.

Unit VII

  • Sequential Circuit Description: Sequential models – feedback model. capacitive model. implicit model. basic memory components. functional register. static machine coding. sequential synthesis

Unit VIII

  • Component Test and Verification: Test bench- combinational circuit testing. sequential circuit testing. test bench techniques. design verification assertion verification.

TEXT BOOKS:

  1. T R. Padmanabhan. B Bala Tripura Sundari. Design through verilog l-IDL. Wiley, 2009-

2 Zainalabdien Navabi. Verilog Digital System Design. TMH. 2nd edition.

REFERENCES:

  1. Fundamentls of Digital Logic with Veilog design by Stephen Brown, Zvonkoc Vranesic. TMH, 2°‘ edition. 2010
  2. Digital Logic Design using Verilog . State machine & synthesis for FPGA. Sunggtt Lee, Cengage Learning .2009
  3. Verilog l-IDL – Samir Palnitkar. 2″‘ Edition. Pearson Education. 2009
  4. Advanced Digital Design with the Verilog HDI – Michel D. Ciietti.

Note :- These notes are according to the r09 Syllabus book of JNTUH.In R13 ,8-units of R09 syllabus are combined into 5-units in r13 syllabus.Click here to check all the JNTU Syllabus books 

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